The present invention relates to a signal processing system having a memory built in an LSI.
In a conventional signal processing apparatus, in order to utilize the bus information such as data and address appearing in the bus in system operation, as fault analysis data in the event of fault taking place in the system, it is stored in an analyzing device such as logic analyzer, or a tracing mechanism as disclosed in the Japanese Laid-open Patent No. 6-187256 is added to the system.
However, owing to the recent advancement in the semiconductor technology, the LSI integrating various function blocks and memories on one chip by large scale is being developed, but in the conventional constitution of signal processing apparatus as mentioned above, since memory interface signal is not issued outside of the LSI, the analyzer cannot be connected, and in the event of fault, necessary information for fault analysis cannot be obtained. Or, to form the tracing mechanism inside the LSI, it requires an exclusive control circuit for fault analysis and an exclusive trace memory, which gives rise to increase in the area of LSI and the cost.
To solve the above problems, the signal processing apparatus of the invention is a signal processing apparatus having a memory and plural blocks for accessing the memory provided inside the LSI, which comprises an arbitration block for receiving each memory use request signal issued from the memory access blocks, arbitrating the memory use right, and accessing the memory, and a trace control block for issuing a memory request signal for storing the memory access history in the memory on the basis of the result of arbitration, and controlling start and end of storing of this access history in the memory and the content of storing, and therefore without requiring any particular control circuit exclusively for fault analysis or exclusive trace memory, necessary information for fault analysis may be obtained easily in the event of fault.
A first aspect of the invention relates to a signal processing apparatus having a memory and plural blocks for accessing the memory provided inside the LSI, being a signal processing apparatus comprising an arbitration block for receiving each memory use request signal issued from the memory access blocks, arbitrating the memory use right, and accessing the memory, and a trace control block for. issuing a memory request signal for storing the memory access history in the memory on the basis of the result of arbitration, and controlling start and end of storing of this access history in the memory and the content of storing, in which the trace control block acts to control start and end of storing of access history necessary when tracing the access history in the memory and the content of storing.
A second aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and the memory access block for storing the access history is selected by setting of the register from outside of the LSI, and therefore by setting the rewritable register as desired from outside of the LSI, the memory access block for storing the access history can be freely selected from outside.
A third aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and a trigger signal is issued outside of the LSI after a specified period determined from outside of the LSI when the value set in the register from outside of the LSI and the access history to be stored are matched, and therefore the trigger signal issued to the outside of the LSI starts operation or terminates operation of an external measuring instrument, and a signal outside of the LSI synchronized with trace process can be also recognized easily.
A fourth aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and the storing function is started after a specified period determined from outside of the LSI when the value set in the register from outside of the LSI and the access history to be stored are matched, and therefore by starting the storing function after the specified period set from outside of the LSI, starting from the trace process to the memory of a specific access history, the subsequent trace process can be left over, and when analyzing a cause of trouble, for example, if the problem triggering access is known, by setting such access, the cause may be easily analyzed.
A fifth aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and the storing function is terminated after a specified period determined from outside of the LSI when the value set in the register from outside of the LSI and the access history to be stored are matched, and therefore by terminating the storing function after the specified period set from outside of the LSI, tracing back from the trace process to the memory of a specific access history, the preceding trace process can be left over, and when analyzing a cause of trouble, for example, if the access after onset of problem is known, by setting such access, the cause may be easily analyzed.
A sixth aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and the access history is stored from a specified position in the memory, and therefore by storing the access history from the specified position in the memory, if trace process of access history in the memory is not necessary, the region of the memory for trace process may be minimized, and it can be used for ordinary function other than trace process, and the storing start position can be changed depending on the required trace storing amount in the event of a trouble.
A seventh aspect of the invention relates to a signal processing apparatus of the first aspect, in which a rewritable register is provided in the trace control block, and the access history is stored to a specified position in the memory, and therefore by storing the access history to the specified position in the memory, if trace process of access history in the memory is not necessary, the region of the memory for trace process may be minimized, and it can be used for ordinary function other than trace process, and the storing end position can be changed depending on the required trace storing amount in the event of a trouble.